1. Field of Invention
The present invention relates to a package structure and a manufacturing method thereof. In particular, the present invention relates to a power semiconductor package structure and a manufacturing method thereof.
2. Related Art
Higher efficiency and higher density are always the demands for the power converters. The higher efficiency indicates the lower power loss, so that this feature can help the power saving. The higher density indicates the smaller product size, so that this feature can achieve the product design of compact and light.
FIG. 1A shows a full-bridge circuit 1A used in the conventional power converter, and FIG. 1B shows a buck circuit 1B used in the conventional power converter. As shown in FIG. 1A, the full-bridge circuit 1A includes four field-effect transistors 11. The four field-effect transistors 11 are divided into two groups and are alternately turned on/off for performing the rectifying function. As shown in FIG. 1B, the buck circuit 1B includes two field-effect transistors 11, and it can convert the voltage by switching the field-effect transistors 11. As a result, the power semiconductor element is one important factor for the efficiency of the power converter.
In practice, the conventional full-bridge circuit 1A and buck circuit 1B include four and two separated field-effect transistors 11, respectively, which are electrically connected through the wires or traces of the circuit board. However, this connection has the issues of poor usage in space and obvious parasitic effect.
In order to improve the above issues, a power semiconductor package structure 2A as shown in FIG. 2A is disclosed. The power semiconductor package structure 2A includes a lead frame 21, a plurality of chips 22, a plurality of wires 23, and a molding compound 24. The chips 22 are arranged in parallel on the pads of the lead frame 21, and each chip 22 is connected to other chip(s) 22 and the corresponding lead through the wires 23. The molding compound 24 covers the chips 22, wires 23 and a part of the lead frame 21.
However, the above technologies of surface integration and wire bonding still have many drawbacks. For example, the conventional field-effect transistor is commonly the vertical structure, and the electrode of the source thereof is usually formed by aluminum evaporation. The thickness of the aluminum pad is within several tens micrometers. In order to perform the following surface brazing soldering and metallization, the thickness of aluminum pad is usually about 5 μm. Since the thickness of the aluminum pad is very small, the lateral resistance is relatively large. Taking a 1 cm×1 cm chip as an example, the resistance between two opposite sides of the chip is up to 5.3 mΩ. In addition, due to the limitation of the wire bonding process, the contact surface between the wire and the source can not cover most area of the source (usually less than 70%). Moreover, since the lateral resistance of the chip is larger, the current distribution between the source and drain of the chip is non-uniform, which is different from the ideal situation, and the current may be concentrated at some points. Besides, the resistance of the wire is usually larger, so the current parasitic effect is very obvious. In addition, the integration level of the surface integrating process can still be improved. Thus, a better solution is desired.
In order to reduce the size of the package structure, a stacked package structure is disclosed. As shown in FIG. 2B, a power semiconductor package structure 2B includes a lead frame 21, a plurality of chips 22, a plurality of wires 23, and a molding compound 24. In this case, the chips 22 are stacked on the lead frame 21 one by one, and a spacer 25 is configured between every two chips 22 so as to provide a predetermined height between the chips 22. Accordingly, the wires 23 can electrically connect the pads of the chips 22 to the pads of the lead frame 21. The molding compound 24 covers the chips 22, the wires 23 and a part of the lead frame 21.
Although the power semiconductor package structure 2B, for packaging multiple chips 22, has the benefit of a smaller size than the power semiconductor package structure 2A, it has a drawback of a difficulty on electrically connecting the pads of the chips 22 and the lead frame 21 due to the stacked structure. In addition, the gaps between the electrodes of the chips 22 must be completely covered by the molding compound 24 so as to achieve the desired isolation and prevent the undesired bubbles, which may decrease the reliability of the package. When the top chip 22 totally covers the gap, the flowing channel for the molding compound 24 becomes narrower. This may make the flowing/filling of the molding compound 24 more difficult so as to form some pores or bubbles, thereby decreasing the reliability of the package structure. Thus, the mold flow design is very important, and some special auxiliary processes, such as an underfill dispensing process or a vacuum process, are needed. These additional auxiliary processes may increase the complex of the manufacturing processes.
Either the power semiconductor package structure 2A or the power semiconductor package structure 2B uses the wires 23 to connect the chips 22 and the lead frame 21. However, since the resistance of the wires 23 is large, and the contact areas between the wires 23 and the chips 22 or between the wires 23 and the lead frame 21 are small, the obvious parasitic effect and current non-uniform may occur. Accordingly, the ripple of the component is increased, or the switching speed of the component is affected, which dramatically increases the on loss and switching loss. This can affect the properties and efficiencies of the power semiconductor package structures 2A and 2B.
Therefore, it is an important subject of the present invention to provide a power semiconductor package structure that has increased reliability and reduced parasitic effect, thereby enhancing the efficiency thereof.